Inside China’s 3D‑stacked AI chip bet under U.S. export controls

What Changed and Why It Matters

A Chinese AI chip startup just emerged from stealth with a simple thesis: win on packaging, not process.

The move signals a broader pivot in China’s semiconductor playbook. With EUV tools and cutting‑edge GPUs restricted, designers are leaning into 3D hybrid bonding and chip stacking to extract performance from mature nodes.

“With EUV lithography tools restricted, Chinese AI chip designers are betting on 3D hybrid bonding and stacking technology to bypass limits.”

Here’s the part most people miss: this isn’t just geopolitics. It’s the post‑Moore’s Law pattern everywhere. When transistors won’t shrink fast enough, you stack dies, move memory closer to compute, and claw back bandwidth. That’s where AI systems bottleneck today.

The Actual Move

What happened across the ecosystem:

A China‑based AI chip startup exited stealth, positioning 3D stacking as its core path to competitive accelerators under export controls. The company’s pitch: dense on‑package memory and logic‑on‑logic stacking via hybrid bonding to reduce data movement costs.
Chinese chip designers and packagers are openly pushing 2.5D/3D integration—chiplets, TSVs, and hybrid bonding—to achieve “node‑like” gains without EUV.
Commentary around Nvidia’s China‑specific GPUs underscores the demand shock and regulatory overhang. Reports suggest certain China‑targeted SKUs have been paused or reworked, widening the opening for domestic alternatives.
Research context backs the strategy. Academic work on 3D AI chips shows how stacking compute and memory can break the memory wall that strangles large‑model training and inference.

“Currently, memory capacity is insufficient to support the most advanced NLP models… we present a 3D AI chip… with stacked memory for higher bandwidth.”

Zoom out and the pattern becomes obvious: rather than chase 5nm or 3nm, China is trying to turn advanced packaging into its performance engine.

The Why Behind the Move

This is a builder’s workaround to structural constraints. Here’s how the strategy maps.

• Model

3D hybrid bonding, logic‑on‑memory and logic‑on‑logic stacks, and chiplets connected at fine pitch. Performance comes from bandwidth and locality, not just clocks and nodes.

• Traction

AI workloads are memory‑bound. Co‑locating memory with compute reduces off‑chip hops. Even legacy‑node logic can punch above weight when you cut data movement.

• Valuation / Funding

Capital shifts from EUV chases into packaging, bonding, and OSAT capacity. Expect funding to target bonding tools, thermal management, and packaging‑aware design flows.

• Distribution

Domestic cloud and OEMs need supply alternatives. If stacked parts hit “good‑enough” training/inference metrics with strong availability, they’ll land design wins—even if peak FLOPs trail frontier GPUs.

• Partnerships & Ecosystem Fit

Winners will stitch together:

local fabs on mature nodes,

OSATs for 2.5D/3D (hybrid bonding, TSV),

domestic memory vendors (HBM or stacked SRAM/DRAM),

EDA/IP tuned for chiplets and thermal‑aware floorplanning.

• Timing

U.S. rules accelerated the shift. At the same time, AI models are scaling memory faster than compute. The window for packaging‑led gains is wide open right now.

• Competitive Dynamics

Nvidia still leads on software, ecosystem, and HBM3E supply.
Chinese vendors can compete on availability, cost, and vertical integration.
If stacked designs deliver high effective bandwidth and better TCO per token, procurement shifts—especially in China’s regulated sectors.

• Strategic Risks

Thermal density and yield: stacking multiplies heat and defect risks.
Toolchain chokepoints: hybrid bonding and metrology tools are mostly non‑Chinese; they could face future controls.
Memory supply: HBM is scarce and geopolitically exposed; SRAM‑heavy stacks hit area limits.
Software stack: without robust kernels, compilers, and model‑parallel libraries tuned for stacked memory, hardware wins won’t translate.

“3D stacking is a curve‑around move in a post‑Moore’s world. The upside is real—but so are the thermal and toolchain traps.”

Note on “4nm‑class” claims by stacking legacy nodes: treat as marketing shorthand for system‑level performance. Packaging can approximate some benefits, but it does not change transistor density.

What Builders Should Notice

Constraints are design inputs. Architecture beats wishful process roadmaps.
Bandwidth is the bottleneck. Move memory closer and you change the game.
Packaging is now product. Treat bonding, thermals, and yield as core R&D.
Software decides winners. Build kernels and compilers for stacked topologies.
Expect policy to chase packaging. Diversify tools and suppliers early.

Buildloop reflection

Every market shift begins as a packaging choice that looks like a workaround.

Sources

South China Morning Post — Chinese AI chip start-up exits stealth mode, bets on 3D stacking to bypass US controls (AMP) (https://amp.scmp.com/tech/tech-trends/article/3359336/chinese-ai-chip-start-exits-stealth-mode-bets-3d-stacking-bypass-us-controls)
Pandaily (X) — Chinese AI Chip Makers Turn to 3D Stacking for a ‘Curve-Around’ (https://x.com/thePandaily/article/2071796983526740119)
LinkedIn — AI Chips Get a Boost with 3D Stacking (https://www.linkedin.com/posts/robertquinn2020_semiconductor-supplychain-geopolitics-activity-7432858786899369984-_s4B)
YouTube — China’s Next AI Shock Is Hardware (https://www.youtube.com/watch?v=k_bHtx_e-SU)
First Squawk (X) — Chinese AI chip start-up emerges from stealth, uses 3D stacking (https://x.com/FirstSquawk/status/2073621477392568673)
EconomyAC — China’s Chip-Stacking Move That Breached the U.S. 14… (https://economy.ac/news/2025/11/202511284344)
arXiv — Breaking the Memory Wall for AI Chip with a New Dimension (https://arxiv.org/pdf/2009.13664)